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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple style='word-wrap:break-word'><div class=WordSection1><p class=MsoNormal>Thanks Terry,<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>I am using Vivado/Vitis/HLS 2020.2 and getting ok with the toolchain. On my SEEED Studio Spartan Edge Accelerator, the board designer has included TI DAC7311 which is a single-input 12-bit DAC at 3V3 output levels. Can I add the schematics to tacos BB mailing list – is that permitted?<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>The board is obviously pre-wired, and made in qty, and cheap ! so I would like to use it. From what I can infer from the data sheet of the device, this is my guess:<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>DDS IP from XLINX (Spartan-7 FPGA)<o:p></o:p></p><p class=MsoNormal>Parallel to serial conversion using (?? SERDES ??) IP from XLINX (Spartan-7 FPGA) to external pins<o:p></o:p></p><p class=MsoNormal>Connection to TI DAC7311<o:p></o:p></p><p class=MsoNormal>Conversion to Analog output.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>The DAC is rated up to 50 MHz .. but that refers to the bits/second of the data transmission, right? For actual RF modulation, that bitstream (waveform) would have to be mixed to the carrier frequency I am roughly sure (asking for confirmation). At that stage, could we then transport a 9.6kbps data stream on say a 144-145 MHz carrier? <o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Samudra N3RDX<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b>From:</b> Terry Fox <tfox@knology.net> <br><b>Sent:</b> Sunday, February 21, 2021 11:02 PM<br><b>To:</b> samudra.haque@gmail.com; tacos@amrad.org<br><b>Subject:</b> Re: design / development question FPGA (Xilinx), DDS and RF output<o:p></o:p></p></div></div><p class=MsoNormal><o:p> </o:p></p><p>I did exactly that a number of years ago, using a Digilent Nexys2 in Verilog. I made a rough signal generator, and a DUC to match the Charleston SDR. I wrote at least the DUC in an AMRAD newsletter article, probably around 2010 or so. IIRC, the D/A chip was the famous AD9744, which almost everyone used. 200MHz clock rate and 12 bit DAC.<o:p></o:p></p><p>Terry, N4TLF<o:p></o:p></p><div><p class=MsoNormal>On 2/20/2021 7:15 PM, <a href="mailto:samudra.haque@gmail.com">samudra.haque@gmail.com</a> wrote:<o:p></o:p></p></div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><p class=MsoNormal>I’m trying to expand my skillset (self-education) by writing a FPGA code block that uses a DDS core IP to produce waveforms. I’m interested In producing up to VHF (2m band) CW and BPSK waveforms if I can. <o:p></o:p></p><p class=MsoNormal> <o:p></o:p></p><p class=MsoNormal>I have access to Zynq7010 and Spartan7 development boards – Any recommendations for a DAC chip that I can use in tandem with this FGPA device?<o:p></o:p></p><p class=MsoNormal> <o:p></o:p></p><p class=MsoNormal>I’ll custom wire a interface for this project. <o:p></o:p></p><p class=MsoNormal><br><br><o:p></o:p></p><pre>_______________________________________________<o:p></o:p></pre><pre>Tacos mailing list<o:p></o:p></pre><pre><a href="mailto:Tacos@amrad.org">Tacos@amrad.org</a><o:p></o:p></pre><pre><a href="https://lists.amrad.org/mailman/listinfo/tacos">https://lists.amrad.org/mailman/listinfo/tacos</a><o:p></o:p></pre></blockquote></div></body></html>