Emerging Design to Compete with FPGAs?

[Frank Gentges]

Tacoistas,

An emerging architecture is being promoted to compete with the FPGAs for some applications.  It seems to have some merit for signal processing but several issues have to be resolved.  See attached which was on the fpgagurus by edn.

First, the programming of the RISC cores has to be easy for users.  I remember the Transputers which were easy to interface to each other in a mesh of processors.  But they were simple stack machines that were programmed in "Occam".  The average user was left with a huge learning curve with a very different kind of processor.  A few very nice systems were designed for this but not enough systems were built to get the silicon foundry up to an economical scale.

Second,   it is not clear if enough chips are going to be produced to let everyone have a chance to try them out.  Look at the widespread availability and low cost of PIC chips and how they have found their way into so many products.  Somehow, this new design needs to be available and companies will feel they are not only available but they will be available in the future as products using them mature in sales.

I have found the FPGA vendors have done a good job of making the design software available and a wide set of chip designs for applications.  The FPGAs have a real head start on whatever might try to compete.  The concept of many cores on a chip is attractive.   We will have to see how this all sorts out.

Frank K0BRA

Published on FPGA Gurus (http://www.fpgagurus.edn.com)Assault on TigerSHARC in its Home Domain

By gjones
Created 2011-05-06 08:48
Author: 
Loring Wirbel [1]
Publish Date: 
May 6, 2011
Andreas Olofsson, a key engineer in Analog Devices Inc.’s TigerSHARC program, was tired of seeing high-end floating-point DSPs from ADI and Texas Instruments Inc. fail to snare design wins because of the chips’ complexity of programming. Three years ago, when Olofsson left ADI to found Adapteva (http://www.adapteva.com/index.php [2]), fixed-point DSPs were being displaced by FPGAs in wholesale fashion, but most FPGAs did not offer performance close enough to take on floating-point, vector-based designs. At the same time, existing high-end DSP devices did not offer a solution, due to both cost and complexity.

At the recent Embedded Systems Conference, Olofsson, now CEO of Adapteva, was there to show some first silicon introduced in conjunction with investor BittWare Inc. (http://www.bittware.com [3]), and to let the world know he was out to make friends in the FPGA community, not challenge such vendors head-on. Adapteva, he said, took an unorthodox path to silicon, surviving in its first two years on angel investments and a small design team. A year ago, BittWare served as majority investor for the company’s Series A funding.

The Adapteva team has developed a scalable architecture of 1 to 4,096 RISC blocks on a single silicon die, connected in a shared-memory mesh that borrows some concepts from the Inmos Transputer of the early 1990s. But while Transputer relied on a dedicated programming language called Occam, Adapteva’s architecture, nicknamed “Epiphany,” uses common tools such as ANSI C, GNU, and Eclipse. BittWare is directly selling its own version of the Adapteva chip, a 16-core device called Anemone.

“It is not our intention to sell silicon directly,” Olofsson emphasized. “We want to license our designs, maybe to OEMs, maybe to microprocessor vendors, but we think particularly this could be a co-processor for existing FPGAs.”

First-pass news reports of the architecture emphasized its potential use in smartphones, but given the fact that most designs would require two baseband/control-plane processing chips, such applications seem like overkill (http://www.pcworld.com/article/226984/chip_maker_adapteva_aims_to_speed_up_smartphones.html [4]). Olofsson said that a more intriguing use of parallel vector arrays might come in intelligence and radar, medical imaging, and similar applications where parallel cores needed to take on some DSP heavy lifting.

Each core in the Adapteva architecture is a superscalar 1-GHz RISC machine. The cores are linked through a shared-memory fabric with up to 64 Kbytes of local memory at each processor node. Network bandwidth is 8 Gbytes/sec per processor, and independent DMA controllers are distributed across the mesh.

Adapteva’s scaling guide for its mesh certainly gives its partners maximum flexibility in choosing numbers of cores and underlying process technology used in chips based on the Epiphany architecture. But the very name “coprocessor” calls up some skepticism in an industry hung up on single-chip SoC devices. This is where having a small Epiphany array implemented inside a large FPGA (or outside, in a 3D hybrid package) might provide best of both worlds. FPGA vendors at the show said off the record that the Adapteva architecture looked intriguing, but that it might make sense to see how the initial standalone chip offered by BittWare is accepted in the market, before committing to a partner program with Adapteva.