New post on SDR-NET

[WB4JFI]

Who am I really???  N4TLF - NOT WB4JFI anymore.....

-----Original Message----- 
From: Terry Fox
Sent: Friday, June 12, 2015 8:24 PM
To: tacos at amrad.org
Subject: New post on SDR-NET

>From Terry, WB4JFI
I just posted this on the new SDR-NET Google group:

A big welcome to Pavel, who joined this new SDR group today.  Pavel has
written code to make the Red Pitaya (RP) an SDR receiver, and is working on
finishing his Red Pitaya transceiver app.  He has also written an interface
DLL that works with HDSDR and SDR Sharp under Windows.  The board interfaces
to the host computer via Ethernet.  His updated code and instructions can be
found at:
http://pavel-demin.github.io/red-pitaya-notes/sdr-receiver/

In testing Pavel's SDR app for the RP, I found that I can see signals as
weak as -113dBm on the spectrum display when running either HDSDR or SDR
Sharp.  There is some small growth in the nearby spectrum at about -40dBm or
stronger, which is an indication of phase noise of the main oscillator.  The
RP now does not overload until about +5dBm, at a 50kHz bandwidth setting.

The Red Pitaya is a small board that contains a Xilinx Zynq SOC processor,
with a two-channel, 14-bit, 125Ms/s ADC and a two-channel, 14-bit, 125Ms/s
DAC.  It also has lower-speed ADCs and DACs, an Ethernet interface, a couple
of USB ports, and some GPIO pins.  The RP was originally on Kickstarter for
about $500, and still sells for that price at some places.  The nice thing
is that Elektor magazine is selling them at about half-price, $250, give or
take, depending on if you are a subscriber.

The RP is billed as a test equipment replacement, and there are several apps
for it that are downloadable from the Red Pitaya website
(www.redpitaya.com).  Since the sample rate is only up to 125Ms/s, don't
expect to use these apps for signals above about 3-4MHz or so.  The apps
include two channel oscilloscopes, two channel signal generator, two-channel
spectrum analyzer, LCR meter, and others.

Several of us in AMRAD have looked at the RP as a possible SDR platform,
since it has all the necessary goodies.  Pavel has connected the dots, and
made an actual working SDR out of the RP.  After some testing, we found one
issue with overloading, which Pavel has already fixed.

Since there are no filters on the RP front end, it digitizes the whole
0-62.5MHz range through the ADC.  This leads to a number of possibilities
down the road, such as a multi-band receiver.  Because there are actually
two channels of ADC sharing the same clock, diversity reception with
different antennas is also possible.  The biggest limitation is probably the
FPGA fabric size inside the small Zynq processor used.

The Zynq is a pretty neat design.  It has some FPGA fabric (called the PL)
around a dual-core Arm Cortex A9 processor (the PS).  There are also DSPs
and multipliers in the FPGA fabric.  Definitely worth keeping an eye on this
Zynq family.  The Parallella board also uses a Zynq, and if you were lucky
enough to be in the Parallella Kickstarter campaign, you (eventually)
received a board with a slightly larger Zynq (the 020 versus the 010 on the
RP).

Some of us are deep into learning about the Zynq chip, so we can program
them.  Being a complicated part, it takes a while to understand.

There will be more information on the RP, the Zynq, and other SDRs as we
spend time getting to know them better.

Meanwhile, welcome again Pavel, and thanks for your work!
73, Terry, N4TLF








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