design / development question FPGA (Xilinx), DDS and RF output

[samudra.haque at gmail.com]

The longer answer is : I'm learning in stages. There is so much to absorb. Getting there. In a direct design such as you describe, if the clock was setup to produce say 144-146 MHz, and we write HDL (or write HLS > HDL) using a simulator I guess it would show up as a short repeated bitstream of square waves?

Can I ask for a suggestion on how I  can simulate it using spice?  OTOH I am wondering which filter calculator might be useful to generate industry compatible part values - I see a few listed on google search. Or, are filter blocks available from a vendor if I wanted to create a board for testing?

Conceptually since the pulse train would be square waves would I need to use a LPF followed by a HPF stage to allow just the desired carrier to get through, or only LPF ? 

73 

Samudra N3RDX



-----Original Message-----
From: Tacos <tacos-bounces+samudra.haque=gmail.com at amrad.org> On Behalf Of kf4hcw
Sent: Monday, February 22, 2021 11:56 AM
To: tacos at amrad.org
Subject: Re: design / development question FPGA (Xilinx), DDS and RF output

On 2/20/21 7:15 PM, samudra.haque at gmail.com wrote:
> I’m interested In producing up to VHF (2m band) CW and BPSK waveforms 
> if I can.

I'm forced to wonder -- since any dac will also require filtering and your goal is simply bpsk, why not just output a binary stream at the carrier frequency on a pin and then filter it until it loses it's spurs?

_M

--
kf4hcw
Pete McNeil
lifeatwarp9.com/kf4hcw

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