on another topic...

[Robert Stratton]

That sounds like a spiffy platform. I might be interested in those as  
well. I'm having far too much fun with the TI EZ430-Chronos though I'm  
having to wrap my mind around the MSP430 view of the universe.

--Bob S.

>
>
>
> mo at ccr.org (Mike O'Dell) writes:
>
>> i had a chat with the CEO of a firm in Montreal who makes
>> a multi-core DSP which uses asynchronous logic in the
>> DSP cores. the net result is incredible processing
>> power with *tiny* power consumption. their new 24-core
>> chip can do 64-72 users of G3/HSDP baseband processing
>> (for cell sites) running at just a smidge over 2 watts.
>> the cores themselves run at about 1.2-1.5GHz "logical
>> clock speed" (since the logic in the cores is asynchronous,
>> there is no "clock" in the usual sense for the cores.
>> there is clock for the TDM interfacing at the edge
>> of the part).
>>
>> there's also an ARM A11 in there, too, just for giggles.
>>
>> the best part is the interfacing - it has a GigE port
>> integral to the chip, a PCIe interface, and high-speed
>> serial ports designed for zero-glue interfacing to the
>> high-speed ADCs used for cellular baseband processing.
>> (Does the name Analog Devices ring a bell?)
>>
>> i'm thinking this could do something like a Quicksilver
>> type SDR *without* needing the fpga and put the entire
>> receiver in the chip, demod software and all, with just
>> the ADC on the front end.
>>
>> i'm going to explore swinging some dev kits if people
>> would like to goof on this.
>>
>> 	-mo

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